1. Field of the Invention
This invention relates generally to the field of pipelined computation and, more particularly, to a system for saving the state of programmable registers in a computational pipeline.
2. Description of the Related Art
The principle of arranging multiple computational units in a series to form a pipeline is well known. Each computational unit Uk in the pipeline receives input data Dk, performs a corresponding set of one or more operations on the data Dk to obtain output data Dk+1. Computational unit Uk may forward its output data Dk+1 to a next computational unit Uk+1, or, to some system external to the pipeline in the case where Uk is the last computational unit in the pipeline. The first computational unit U0 in the pipeline receives initial data D0. The last computational unit UN in the pipeline outputs final results DN+1. The pipeline may operate in a clocked fashion, where each computational unit Uk operates on a new set of input data Dk in every pipeline clock cycle.
In modem pipelines, the computational units have programmable registers that allow the functionality of the computational units to be modified. Furthermore, multiple processes may use the pipeline in a time-shared fashion. Before switching from one process to another, the values of the programmable registers in the computational units may need to be saved because the next process may use a different set of values for the programmable registers. Even in situations where the pipeline is not shared between multiple processes, there may be a variety of reasons for reading values stored in the computational pipelines. Thus, there exists a need for a system and method which efficiently provides for the reading of stored values (e.g. register values) from the computational units.